In the field of electronic component packaging numerous problems exist. For example, the bonding of conductive elements of a leadframe to a semiconductor chip often results in chip passivation fractures during the bonding process. These fractures may occur due to excessive bonding force, misalignment occurring during the bonding process, or inadequate standoff means to prevent the conductive elements from being undesirably compressed against the semiconductor chip. Other fracture phenomena occur during thermal cycling of components and result in poor quality products which are either rejected or which perform improperly. Further problems in the packaging field include an inability to provide fine pitch geometries at various levels of chip packaging to achieve the area utilization demands of higher density devices. These all represent particularly long-standing problems and constant challenges in the packaging field, but ones which find solutions in the present application in various ways.
Wasteful, inefficient, or unnecessary processing steps in the production of semiconductor chips and other electronic components accounts for substantial redundancy in the packaging field. Moreover, as more complicated devices require additional processing steps such devices become increasingly susceptible to processing errors which may lead to poor performance and low yields. In the field of semiconductor chip production alone, the volume of chips manufactured results in substantial numbers of improperly packaged devices due to processing problems. Moreover, it is quite common to experience low production yields in the initial production phases of newly designed chips. By streamlining and minimizing the steps required in a chip production process, efficiencies combine to provide greater overall yield percentages.
Yet a further problem identified in the prior art of electronic component packaging includes devices which are manufactured having inefficient utilization of chip surface areas. Non-efficient structure in the packaging field is tantamount to reducing the performance capabilities of the electronic device. Rather, more efficient use of existing space on an electronic component is the touchstone to improved performance. Therefore, the more efficient use of the valuable chip surface area on electronic components permits advanced capabilities, such as improved spacing and pitch geometries. The present invention provides immediate improvements affecting the production and operation of electronic devices and assemblies which overcome these problems identified above.
Various bonding techniques exist which permit bonding of electronic components. These bonding techniques include the use of relatively hard-bonding material, such as gold, and soft-bonding material such as solder compositions. Although the use of solder compositions is known in the art, such compositions have generally been used as formations which are placed on semiconductor chip devices during the chip production process. Various compositions of solder have been used, including tin-lead compositions. Commonly, soft solder material is plated onto interface regions of components as final processing steps prior to final component testing. It has now been found valuable to apply soft solder material, in the form of preformed solder bumps, to other structures in the packaging process. One example of another structure is the conductive elements of a leadframe. By placing preformed solder bumps on the conductive elements of a leadframe, substantial efficiencies in the overall production, packaging, and testing cycle occur. Alternately, the present invention provides improved solder compositions for strengthening the bonding capability of solder bumps preformed onto semiconductor chips.
Therefore, the present application describes improved packaging and bonding of electronic components to achieve optimum signal fidelity, fine pitch geometries, improved yield, greater reliability, and various manufacturing efficiencies. The improvements comprise several unique embodiments of tape leadframe technology, solder bump transfer and bonding techniques, and preferred bonding and fluxing material compositions.